Since the invention of the integrated circuit (IC), the semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components. For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. As the demand for even smaller electronic devices has grown, there has grown a need for smaller and more creative packaging techniques of semiconductor dies.
Two types of packaging techniques for die assembly are used. The older and mature technique is wire bonding (WB) where the die is back bonded and wires connect from the top (face) of the die to the substrate. The newer technique is flip chip (FC) bonding, where the chip is bonded face down on the substrate and the interconnection is accomplished with a small solder ball or bump.
There is an increased awareness in the semiconductor industry that assembly and packaging is an essential and integral part of the semiconductor product. Packaging techniques have become a critical competitive factor in many market segments, since it affects operating frequency, power, reliability, and cost. As a result of rapidly emerging technologies and applications, the boundaries between semiconductor, packaging, and system technologies are no longer clear; they must all be considered concurrently in a system-level approach in order to optimize the substrate design and package techniques.
Substrates have become the most expensive element of electronic packages while at the same time limiting package performance. Ceramic, multi-layer substrates have always been very expensive but they allow for a great deal of design freedom e.g. integration of passives. The drawbacks are a high dielectric constant and a very low coefficient of thermal expansion (CTE) as compared to printed circuit boards (PCB) but closely matched to the silicon die. On the other hand, organic substrates have a CTE which is matched to PCBs but is significantly larger than that of the silicon die. Organic substrates were originally introduced to significantly reduce the cost of packaging by taking advantage of low cost PCB manufacturing technology, materials and scale. Organic substrates can be subdivided further, such as laminate substrates used for plastic ball grid array (PBGA), or build-up substrates typically used for Flip Chip die (FCBGA). Sequential build-up (SBU) laminate substrate technology is now the technology of choice for high density, high-performance silicon packaging. For example, SBU technology was selected by Intel for flip-chip packaging.
PBGA substrates come in a few simple configurations: two layers (2L), four layers (4L) and six layers (6L) of circuitry which are interconnected by plated through holes (PTH). An SBU laminate substrate is composed of three distinct technology elements: the surface finish for soldering and adhesion, build-up layers that contain most of the wiring, and a core layer, which provides mechanical strength. How to optimize the core layer design of a substrate for efficient packaging is a problem.